1. Field of the Invention
The present invention relates to a digital timing unit for timing data processing systems or units thereof, particularly memory units.
2. Description of the Prior Art
It is known that the operation of data processing systems and of memory units coupled to them must be precisely timed. It is also known that, notwithstanding the project accuracy, some timing problems may occur during the prototype testing which require timing modifications. Additionally, because of the fast evolution in electronic technologies the speed performances of several integrated components are rapidly increasing. Because of the component evolution, therefore, a full exploitation of component performances requires matching of the timing to such component evolution. For instance, integrated memory circuits, available on the market in subsequent periods, may have the same external features (number of interconnecting pins, relative layout, signal transferred from a determined pin) but higher and higher working speed. Such integrated components are generally mounted on a supporting printed circuit board, which also includes the timing unit suitable to control such integrated components. Because of the evolution of memory component performances it is therefore necessary to redesign the timing unit and the supporting printing circuit unless the timing unit can be modified.
In the prior art electromagnetic delay lines with intermediate taps have been used as a basic element of the timing units. Such delay lines imposed fixed timing within each cycle, or the timing can be changed in a discrete way by selecting one among several possible intermediate taps. Moreover the attainable timing accuracy is limited by the relatively large tolerances of such components. In fact these components, even though unaffected by temperature changes and free from aging phenomena, may have a large spread in delay time even though they are of the same type and with the same nominal specifications.
Other timing units have been used which make use of an oscillator for the generation of basic timing pulses with predetermined frequency and have a counter which is advanced by the basic pulses. Timing pulses of a variable length multiple of the basic pulse period, can be obtained from the counter outputs, by means of suitable decoding logic networks. Moreover the timing can be modified in a continuous way, therefore proportionally modifying the length of all the timing pulses, by changing the oscillator frequency. A relative variation in the pulse length is, however, possible only after modifying the decoding logic network, which involves substantially redesigning the whole timing unit.
In an alternate embodiment disclosed, for example by U.S. Pat. No. 4,249,253, issued Feb. 3, 1981, cascade shift registers may be used instead of the counter. The registers are progressively loaded with a logical/electrical level which propagates through them. Even in this case the timing pulses are obtained from the shift register outputs by means of a decoding logic network with the above mentioned limits, and at the end of a timing cycle, the shift register must be reset to be ready for the subsequent cycle start. The reset operation simultaneously occurs on a great number of cells and involves a sudden current variation in each of the involved cells. The amount of the total current change causes the generation of electrical noise which may affect the correct working of the system logic circuits.
These undesirable effects are overcome by the digital timing unit of the present invention, which offers the following advantages: (a) it permits the generation of very precise timing pulses; (b) it permits the changing of timing pulse length in a continuous proportional way for all the timing pulses; (c) it permits changing the relative timing length of the timing pulses without substantial circuit modifications, the only change being in electrical interconnections; and (d) it does not cause electrical noise because it does not require reset operations.